As semiconductor devices become more highly integrated, a width of a gate pattern within the semiconductor device may be gradually narrowed. However, such a reduction in a width of the gate pattern may increase a resistance of the gate pattern. This may degrade high-speed operation of a transistor. To ameliorate such problems, a method of forming a metal silicide layer having superior conductivity on a gate pattern or a doped region such as a source/drain region has been used.
FIGS. 1 through 3 are example cross-sectional diagrams illustrating a related art method of manufacturing a transistor having a metal silicide layer. FIGS. 4 and 5 are example cross-sectional diagrams illustrating problems that may be caused in the related art method of manufacturing a transistor having a metal silicide layer.
Referring to FIG. 1, gate insulating layer pattern 110 and gate conductive layer pattern 120 may be sequentially stacked on semiconductor substrate 100. Gate conductive layer pattern 120 may include a polysilicon layer. A first ion implantation process may then be performed to form source/drain extension region 131. After that, spacer layer 140 may be formed on the side-walls of gate insulating layer pattern 110 and gate conductive layer pattern 120. A second ion implantation process may be performed to form deep source/drain region 132. Source/drain extension region 131 and deep source/drain region 132 constitute source/drain region 130 of an LDD (Lightly Doped Drain) structure.
Referring to FIG. 2, metal layer 150 may be deposited on a surface (for example, the entire surface) of semiconductor substrate 100. Metal layer 150 may be a titanium (Ti) layer or a cobalt (Co) layer, and may be formed on the surface of semiconductor substrate 100 by a sputtering method.
Referring to FIG. 3, metal layer 150 adjacent to source/drain region 130 of the LDD structure and gate conductive layer pattern 120 may be heat treated. Metal layer 150 may thereby become silicide. As a result, first metal silicide layer 151 and second silicide layer 152 may be formed on gate conductive layer pattern 120 and source/drain region 130 of the LDD structure, respectively. After that, metal layer 150 that is not subject to the reaction may be removed.
Referring to FIG. 4, a spacer insulating layer, e.g., a nitride layer, may not be completely removed, but may remain on source/drain region 130 when forming the metal layer 140. In this case, as indicated by “A” in FIG. 4, the remaining insulating layer may interrupt the formation of second metal silicide layer 152 on source/drain region 130 during the process of forming the metal silicide layer.
Referring to FIG. 5, since non-reacted metal layer 150 may not be completely removed, metal layer residue 150′ may remain on a side surface of spacer layer 140. In this case, as indicated by “B” in FIG. 5, a bridge may be generated between first metal silicide layer 151 and second metal silicide layer 152, which may cause a malfunction of the transistor.